As reported in Takemura, et al., “2 Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching,” IEEE (2007) (Takemura, et al.), magnetic tunnel junction with MgO tunneling barrier which offers the resistance ratio of “1” state to “0” state—Tunnel Magneto-Resistance, (TMR ratio)—over 100% (up to 472%) and reduced threshold current (write current) density under 500 uA per cell (down to 100 μA), has made the spin-transfer torque writing type memory a viable and serious candidate for low power non-volatile RAM, or universal memory. According to Takemura, et al., however, there are few reports of circuits and memory-array technology which are appropriate for spin-transfer torque writing and its related reading schemes.
The spin transfer torque [STT] process is reported in Kawahara, T., el al., “Spin-transfer Torque RAM: Review and Prospect,” Micoelectronics Reliability, 52 (2012) 613-627 (herein incorporated by reference) occurs when electrons flow from a pinned layer to a free layer. After electrons pass through the pinned layer, the electrons with the same spin direction as that of the magnetization in the pinned layer mainly remain and the current is spin-polarized. This spin-polarized current exerts STT on the magnetization of the free layer, and when the amount of spin-polarized current exceeds the threshold value, the magnetization of the free layer is switched. In parallel (P) to antiparallel (AP) switching, electrons should flow from the free layer to the pinned layer. After electrons pass through the free layer, the electrons with the same spin direction as that of the magnetization in the pinned layer pass through that layer. However, the electrons with the opposite spin direction is reflected at the boundary between an MgO barrier and the pinned layer and injected into the free layer. This current exerts STT on the magnetization of the free layer, and when the amount of the spin-polarized current exceeds the threshold value, the magnetization of the free layer is switched. In the read operation, the signal voltage in a sense amplifier is defined by the resistance difference between the parallel and antiparallel states and the amount of read current.
It is known that programming of memory cells can be accomplished by changing the phase of materials, i.e., from amorphous to crystalline state. The publication entitled “OUM—A 180 nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications” by Stefan Lai, et al., Intel Corp., Santa Clara, Calif., February 2001, Proceedings of: Electron Devices Meeting, 2001, IEDM Technical Digest International, IEEE Xplore (2001), herein incorporated by reference, discusses the development status of the memory cell element of OUM (Ovonic Unified Memory)—a chalcogenide based, phase-change nonvolatile, semiconductor memory technology involving phase changing materials. OUM is a nonvolatile memory that utilizes a reversible structural phase change between amorphous and polycrystalline states in a GeSbTe chalcogenide alloy material. Because of the very small size, temperature steps required to form the elements do not compromise transistor performance, During the amophizing reset pulse, the temperature of the programmed volume of phase-change material exceeds the melting point which eliminates the polycrystalline order in the material. The crystallizing set pulse is of lower amplitude and sufficient duration (12-50 ns) to maintain device temperature in the rapid crystallization range for a time sufficient for crystal growth.
The publication entitled “A GeSbTe Phase-Change Memory Cell Featuring a Tungsten Heater Electrode for Low-Power, Highly Stable, and Short-Read-Cycle Operations” by N. Takaura, et al, International Electron Devices Meeting; IEEE, 897-900 (2003) (ISBN 0780378725) (herein incorporated by reference, features a Germanium-Antimony-Tellurium (GeSbTe) memory cell with a tungsten heater electrode. The cell has a reset current (50 PA) for the phase-change memory device.